100G QSFP28 AOC

HANSUN Communication HX-QSFP28-AOC1M is a Four-Channel, Pluggable, Parallel, Fiber-Optic 40G QSFP+ SR for 100 or 40 Gigabit Ethernet, Infiniband FDR/EDR Applications. This transceiver is a high-performance module for short-range multi-lane data communication and interconnects applications. It integrates four data lanes in each direction with 100 Gbps bandwidth. Each lane can operate at 25Gbps up to 70 m using OM3 fiber or 100 m using OM4 fiber. These modules are designed to operate over multimode fiber systems using a nominal wavelength of 850 nm. The electrical interface uses a 38 contact edge type connector. The optical interface uses a 12 fiber MTP(MPO) connector.

Applications of 100G QSFP28 AOC

IEEE 802.3bm 100GBASE SR4 and 40GBASE SR4 28G Fiber Channel
Infiniband FDR/EDR

Specifications of 100G QSFP28 AOC

Absolute Maximum Ratings

Parameter	Symbol	Min	Max	Unit
Storage Temperature	HX	-20	85	℃
Case Operating Temperature	T_Case	0	70	℃
Relative Humidity	RH	0	85	%
Supply Voltage	V_CC	-0.5	3.6	V

Recommended Operating Conditions

Parameter	Symbol	Min	Typical	Max	Unit
Case Operating Temperature	T_Case	0	–	70	℃
Humidity	RH	5	–	85	–
Supply Voltage	V_CC	3.13	3.3	3.47	V
Data Rate Per Lane	DR	–	25.78125	–	Gbit/s
Fiber Bend Radius	R_b	3	–	–	cm

Electrical Characteristics

NOTE: The EDR module requires an electrical connector compliant with SFF-8662 or SFF-8672 be used on the host board to guarantee its electrical interface specification. Please check with your connector supplier

Parameter	Symbol	Min	Typical	Max	Unit
Supply Voltage	V_CC	3.15	–	3.45	V
Supply Current	I_CC	–	–	1010	mA
Total Power Dissipation1,2	P	–	–	3.5	W
Transmitter
Differential Input Voltage	V_in	–	–	900	MVP-p
Differential Termination Resistance Mismatch	–	–	–	10	%
Transition Time, 20 to 80%	Tr, Tf	10	–		ps
Receiver
Differential Output Voltage	V_out	–	–	900	MVP-p
Differential Termination Resistance Mismatch	–	–	–	10	%
Transition Time, 20 to 80%	Tr, Tf	9.5	–	–	ps
Bit Error Rate3	BER	–	–	10^-12	–

Note:

Maximum total power value is specified across the full temperature and voltage range
Settable in various discrete steps via the I2C interface
BER=10-12, PRBS 231-1@25.78125Gbps

IEEE 802.3bm 100GBASE SR4 and 40GBASE SR4 28G Fiber Channel
Infiniband FDR/EDR

Module Block Diagram of 100G QSFP28 AOC

Pin Definitions of 100G QSFP28 AOC

Pin	Symbol	Name/Description
1	GND	Ground
2	Tx2n	Transmitter Inverted Data Input
3	Tx2p	Transmitter Non-Inverted Data Input
4	GND	Ground
5	Tx4n	Transmitter Inverted Data Input
6	Tx4p	Transmitter Non-Inverted Data Input
7	GND	Ground
8	ModSelL	Module Select
9	ResetL	Module Reset
10	Vcc Rx	+3.3 V Power supply receiver
11	SCL	2-wire serial interface clock
12	SDA	2-wire serial interface data
13	GND	Ground
14	Rx3p	Receiver Non-Inverted Data Output
15	Rx3n	Receiver Inverted Data Output
16	GND	Ground
17	Rx1p	Receiver Non-Inverted Data Output
18	Rx1n	Receiver Inverted Data Output
19	GND	Ground
20	GND	Ground
21	Rx2n	Receiver Inverted Data Output
22	Rx2p	Receiver Non-Inverted Data Output
23	GND	Ground
24	Rx4n	Receiver Inverted Data Output
25	Rx4p	Receiver Non-Inverted Data Output
26	GND	Ground
27	ModPrsL	Module Present
28	IntL	Interrupt
29	Vcc Tx	+3.3 V Power supply transmitter
30	Vcc1	+3.3 V Power Supply
31	LPMode	Low Power Mode
32	GND	Ground
33	Tx3p	Transmitter Non-Inverted Data Input
34	Tx3n	Transmitter Inverted Data Input
35	GND	Ground
36	Tx1p	Transmitter Non-Inverted Data Input
37	Tx1n	Transmitter Inverted Data Input
38	GND	Ground